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? semiconductor components industries, llc, 2012 july, 2012 ? rev. 0 1 publication order number: NCP1336/d NCP1336a/b quasi-resonant current mode controller for high power universal off-line supplies the NCP1336 hosts a high ? performance circuitry aimed to powering quasi ? resonant converters. capitalizing on a novel valley ? lockout system, the controller shifts gears and reduces the switching frequency as the power loading becomes lighter. this results in a stable operation despite switching events always occurring in the drain ? source valley. this system works down to the 4 th valley and toggles to a variable frequency mode beyond, ensuring an excellent standby power performance. the controller takes benefit of a high ? voltage start ? up current source to provide a quick and lossless power ? on sequence. to improve the safety in overload situations, the controller includes an over power protection circuit which clamps the delivered power at high ? line. safety ? wise, an adjustable timer relies on the feedback voltage to detect a fault. on version b, this fault triggers a triple ? hiccup on the vcc pin which naturally reduces the average input power drawn by the converter. on version a, when a fault is detected, the controller is latched ? off. particularly well suited for adapter applications, the controller features two latch inputs: one dedicated to over temperature protection (otp) which offers an easy means to connect a pull ? down temperature sensor like an ntc, and a second one more classical that can be used to perform an accurate over voltage protection. finally, a brownout pin which stops the circuit operation in presence of a low mains condition is included. features ? quasi ? resonant peak current ? mode control operation ? valley switching operation with valley ? lockout for noise ? immune operation ? internal 5 ms soft ? start ? loss ? free adjustable over power protection ? auto ? recovery or latched internal output short ? circuit protection ? adjustable timer for improved short ? circuit protection ? overvoltage and overtemperature protection inputs ? brownout input ? ? 500 ma/+800 ma peak current source/sink capability ? internal temperature shutdown ? direct optocoupler connection ? 3 s blanking delay to ignore leakage ringing at turn ? off ? extremely low no ? load and standby power ? so14 package ? these are pb ? free devices ? this device uses halogen ? free molding compound typical applications ? high power ac ? dc converters for tvs, set ? top boxes etc ? offline adapters for notebooks http://onsemi.com so ? 14 case 751an suffix o pin connections marking diagram a = assembly location x = a or b wl = wafer lot y = year ww = work week g = pb ? free package (top view) hv bo ovp vcc drv gnd otp opp zcd timer ct fb cs quasi ? resonant pwm controller for high power ac ? dc wall adapters see detailed ordering and shipping information in the package dimensions section on page 25 of this data sheet. ordering information 1 14 NCP1336x awlywwg 1 14
NCP1336a/b http://onsemi.com 2 pin function description pin no. pin name function pin description 1 opp adjust the over power protection a negative voltage applied to this pin reduces the internal maximum peak current setpoint. connecting it to an auxiliary winding through a resistor divider thus performs over power compensation. if grounded, opp is null. 2 otp over ? temperature protection connect an ntc between this pin and gnd pin. pin 2 features an internal current source that biases the ntc. when the ntc pulls the pin down, the circuit permanently latches ? off. 3 timer timer wiring a capacitor to ground helps selecting the timer duration. 4 zcd zero crossing detection connected to the auxiliary winding, this pin detects the core reset event. 5 ct timing capacitor a capacitor connected to this pin acts as the timing capacitor in foldback mode. 6 fb feedback pin hooking an optocoupler collector to this pin will allow regulation. 7 cs current sense this pin monitors the primary peak current. 8 gnd ? this pin is the controller ground. 9 drv driver output this pin is the driver?s output to an external mosfet. 10 vcc supplies the controller this pin is connected to an external auxiliary voltage. 11 bo brownout this pin is the brownout input. 12 ovp over ? voltage protection by pulling this pin high, the controller can be permanently latched ? off. 13 nc ? this pin is omitted for improved creepage. 14 hv high ? voltage input connected to the bulk capacitor, this pin powers the internal current source to deliver a startup current. overcurrent protection on NCP1336 versions auto ? recovery overcurrent protection latched overcurrent protection NCP1336 / a x NCP1336 / b x
NCP1336a/b http://onsemi.com 3 figure 1. typical application example vout hv ? bulk gnd gnd NCP1336 ovp otp bo opp zcd 1 2 3 4 5 6 7 9 10 11 12 13 14 8 + + + vin
NCP1336a/b http://onsemi.com 4 figure 2. internal circuit architecture + ? + ? + ? + ? fb ct ict 1st 2nd 3rd 4th vco + ? + ? zcd laux 10 v esd vth drv 3us pulse + ? 5us timeout 100 ns decimal counter 1 demag clk s r q cs rsense leading edge blanking + ? ilimit + vopp /4 opp leakage blanking + ? ibo noise delay hv vbo + ? + ? vcc t vovp votp s r q noise delay otp timer vdd vdd vdd soft ? start + ? itimerc vdd vcc aux v cc management latch vdd hv hv hv startup rpullup rst fault bo reset drv gate grand reset grand reset grand reset drv gnd ipeak_min = 25% limit clamp soft ? start end ? then 1 else 0 a: latched ipflag vdd iotp ovp + ilimit + ? + ? ss end ss end itimerd s r q ipflag pwm reset pwmreset 234 q q q ct setpoint discharge ct pnok tsd + bo reset bo
NCP1336a/b http://onsemi.com 5 maximum ratings table symbol rating value unit vccmax iccmax maximum power supply voltage, v cc pin, continuous voltage maximum current for vcc pin ? 0.3 to 28 30 v ma vhvmax ihvmax high voltage pin (pin 14) voltage range pin 14 current range ? 0.3 to 500 20 v ma vmax imax maximum voltage on low power pins (except pin 9, pin 10 and pin 14) current range for low power pins (except pin 9, pin 10 and pin 14) ? 0.3 to 10 10 v ma vopp max iopp neg recommended maximum operating voltage on pin opp (pin 1) maximum negative current into opp pin (pin 1) ? 300 2 mv ma v drv(max) maximum drv pin voltage when drv is in high state v cc + 1.0 v r ja thermal resistance junction ? to ? air 120 c/w tj max maximum junction temperature 150 c storage temperature range ? 60 to +150 c esd capability, hbm model (all pins except hv) (note 1) 2 kv esd capability, machine model (all pins except drv) (note 1) 200 v esd capability, machine model (drv pin) (note 1) 160 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection rated using the following tests: human body model 2000 v per jedec standard jesd22, metho d a114e. machine model method 200 v per jedec standard jesd22, method a115a. 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78.
NCP1336a/b http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol rating min typ max unit supply section vcc on v cc increasing level at which the current source turns ? off 14 15 16 v vcc min v cc level below which output pulses are stopped 8 9 10 v vcc reset internal latch reset level ? 5.5 ? v i cc1 internal ic consumption, no output load on drv pin (fsw = 10 khz) ? 1.4 2.0 ma icc1 light i cc1 for a feedback voltage equal to vh vco (internal bias reduction), with c t = 220 pf (corresponding to an fsw of about 20 khz) 1.8 ma icc2 internal ic consumption, 1 nf output load on pin 9, fsw = 65 khz ? 2.5 3.0 ma icc3 internal ic consumption, hiccup phase (vcc min < v cc < vcc on ) ? 0.45 0.6 ma internal startup current source (t j > 0 c) (hv pin biased to 60 vdc) ic2 high ? voltage current source, v cc = 10 v (note 3) 3 6 9 ma ic1 high ? voltage current source, v cc = 0 150 300 550 a v th v cc transition level for ic1 to ic2 toggling point (i hv = 2.5 ma) 0.3 0.7 0.9 v i leak leakage current for the high voltage source, v hv(pin) = 500 vdc 1 12 30 a drive output t r output voltage rise ? time @ c l = 1 nf, 10% ? 90% of a 12 v output signal ? 40 75 ns t f output voltage fall ? time @ c l = 1 nf, 10% ? 90% of a 12 v output signal ? 25 60 ns i source source current capability at v drv = 2 v ? 500 ? ma i sink sink current capability at v drv = 10 v ? 800 ? ma vdrv low drv pin level at v cc close to vcc min with a 33 k resistor to gnd and a 1 nf capacitor to gnd 7.6 ? ? v vdrv high drv pin level at v cc = 28 v with a 1 nf capacitor to gnd (note 3) ? ? 17 v demagnetization input v th input threshold voltage (v zcd(pin) decreasing) 35 55 90 mv v h hysteresis (v zcd(pin) increasing) 15 35 55 mv vc h vc l input clamp voltage high state (i zcd(pin) = 3.0 ma) low state (i zcd(pin) = ? 2.0 ma) 8 ? 0.9 10 ? 0.7 12 0 v v t dem demag propagation delay (v zcd(pin) decreasing from 4 v to ? 0.3 v) ? 150 250 ns c par internal input capacitance at v zcd(pin) = 1 v ? 10 ? pf t blank blanking delay after t on 2 3 4 s t out timeout after last demag transition 4 5.25 6.5 s current comparator i ib input bias current @ 1 v input level on cs pin ? 0.02 ? a i limit1 maximum internal current setpoint ? t j = 25 c ? opp pin grounded 0.76 0.8 0.84 v i limit2 maximum internal current setpoint ? t j from ? 40 c to 125 c ? opp pin grounded 0.744 0.8 0.856 v ipeak_vco percentage of maximum peak current level at which vco takes over (note 4) 22 25 28 % t del propagation delay from current detection to gate off state ? 100 160 ns t leb leading edge blanking duration t j = ? 5 c to +125 c t j = ? 40 c to +125 c 240 240 295 295 350 360 ns 3. minimum value for t j = 125 c. 4. the peak current setpoint goes down as the load decreases. it is frozen below ipeak_vco (ipeak = cst) 5. if negative voltage in excess to ? 300 mv is applied to opp pin, the current setpoint decrease is no longer guaranteed to be linear. 6. ntc on otp pin with r = 8.8 k at 110 c.
NCP1336a/b http://onsemi.com 7 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min rating current comparator opp max setpoint decrease for v opp = ? 300 mv (note 5) 35 37.5 40 % opp s setpoint decrease for opp pin shorted to ground ? 0 ? % timing capacitor vct max maximum voltage on ct capacitor, v fb < vfb t 5 5.5 ? v i ct source current (ct pin grounded) t j = ? 5 c to +125 c t j = ? 40 c to +125 c 18 17.42 20 20 22 22 a vct min minimum voltage on ct, discharge switch activated ? ? 90 mv ct recommended timing capacitor value ? 220 ? pf feedback section r pullup internal pullup resistor t j = ? 5 c to +125 c t j = ? 40 c to +125 c 16 15.5 18 18 24 24 k i ratio fb pin to current setpoint division ratio 3.75 4 4.25 vfb t fb pin threshold under which the ct capacitor is clamped to vct max 0.26 0.3 0.34 v vh 2d fb voltage where 1 st valley ends and 2 nd valley starts (v fb decreasing) 1.316 1.4 1.484 v vh 3d fb voltage where 2 nd valley ends and 3 rd valley starts (v fb decreasing) 1.128 1.2 1.272 v vh 4d fb voltage where 3 rd valley ends and 4 th valley starts (v fb decreasing) 0.846 0.9 0.954 v vh vcod fb voltage where 4 th valley ends and vco starts (v fb decreasing) 0.752 0.8 0.848 v vh vcoi fb voltage where vco ends and 4 th valley starts (v fb increasing) 1.316 1.4 1.484 v vh 4i fb voltage where 4 th ends and 3 rd valley starts (v fb increasing) 1.504 1.6 1.696 v vh 3i fb voltage where 3 rd ends and 2 nd valley starts (v fb increasing) 1.692 1.8 1.908 v vh 2i fb voltage where 2 nd ends and 1 st valley starts (v fb increasing) 1.88 2 2.12 v protections v ovp ovp level 2.79 3 3.21 v tlatch del delay before latch confirmation (noise immunity) 15 20 25 s ilatch internal source current for otp (note 6) t j = ? 5 c to +125 c t j = ? 40 c to +125 c 85 82 93 93 97 98 a ilatch 110 internal source current for otp @ 110 c (note 6) ? 91 ? a v otp fault detection level for otp (note 6) 0.76 0.8 0.84 v vtimfault timer level completion 4.65 5 5.35 v itimerc timer capacitor charging current t j = ? 5 c to +125 c t j = ? 40 c to +125 c 8.5 8.25 10 10 11.5 11.5 a itimerd timer capacitor discharging current 8.5 10 11.5 a timerl timer length, ctimer = 0.1 f typical ? 50 ? ms tss soft ? start duration ? 5 ? ms tsd temperature shutdown 140 ? ? c tsd hys temperature shutdown hysteresis ? 40 ? c 3. minimum value for t j = 125 c. 4. the peak current setpoint goes down as the load decreases. it is frozen below ipeak_vco (ipeak = cst) 5. if negative voltage in excess to ? 300 mv is applied to opp pin, the current setpoint decrease is no longer guaranteed to be linear. 6. ntc on otp pin with r = 8.8 k at 110 c.
NCP1336a/b http://onsemi.com 8 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min rating brownout protection vbo brownout level 0.744 0.8 0.856 v ibo hysteresis current, v bo(pin) < vbo t j = ? 5 c to +125 c t j = ? 40 c to +125 c 9 8.65 10 10 11 11 a tbo del delay before bo confirmation (noise immunity) 11 17 23 s ibo bias brownout input bias current ? 0.02 ? a 3. minimum value for t j = 125 c. 4. the peak current setpoint goes down as the load decreases. it is frozen below ipeak_vco (ipeak = cst) 5. if negative voltage in excess to ? 300 mv is applied to opp pin, the current setpoint decrease is no longer guaranteed to be linear. 6. ntc on otp pin with r = 8.8 k at 110 c.
NCP1336a/b http://onsemi.com 9 application information NCP1336 implements a standard current ? mode architecture operating in quasi ? resonant mode. thanks to a novel circuitry, the controller prevents valley ? jumping instability and steadily locks out in selected valley as the power demand goes down. once the fourth valley is reached, the controller continues to reduce the frequency further down, offering excellent efficiency over a wide operating range. thanks to a fault timer combined to an opp circuitry, the controller is able to efficiently limit the output power at high ? line. ? quasi ? resonance current ? mode operation : implementing quasi ? resonance operation in peak current ? mode control, the NCP1336 optimizes the efficiency by switching in the valley of the mosfet drain ? source voltage. thanks to a novel circuitry, the controller locks ? out in a selected valley and remains locked until the output loading significantly changes. this behavior is obtained by monitoring the feedback voltage. when the load becomes lighter, the feedback setpoint changes and the controller jumps into the next valley. it can go down to the 4 th valley if necessary. beyond this point, the controller reduces its switching frequency by freezing the peak current setpoint. during quasi ? resonance operation, in case of very damped valleys, a 5 s timer adds the missing valleys. ? frequency reduction in light ? load conditions : when the 4 th valley is left, the controller reduces the switching frequency which naturally improves the standby power by a reduction of all switching losses. ? overpower protection (opp) : a negative voltage applied on opp pin is directly added to the internal peak current setpoint. if this voltage is created from an auxiliary winding with flyback polarity, a direct image of the input voltage is subtracted from the internal clamp, thus reducing the peak current at high line. if the opp pin is connected to ground no compensation is performed. ? internal high ? voltage startup switch : reaching a low no ? load standby power represents a difficult exercise when the controller requires an external, lossy, resistor connected to the bulk capacitor. thanks to an internal logic, the controller disables the high ? voltage current source after startup which no longer hampers the consumption in no ? load situations. ? internal soft ? start : a soft ? start precludes the main power switch from being stressed upon start ? up. its duration is fixed and equal to 5 ms. ? otp input : thanks to an internal current source, the controller allows the direct connection of an ntc to ground. as soon as the pin is brought below votp by the ntc, the circuit permanently latches ? off. during soft ? start, the otp comparator is masked to allow the voltage on pin otp to rise above votp. ? ovp input : thanks to an internal bias resistor to ground, the controller allows the direct connection of a zener diode (or a resistor divider for improved accuracy) to a monitored voltage. as soon as the pin is brought above vovp, the controller latches ? off. ? short ? circuit protection : short ? circuit and especially over ? load protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (where the auxiliary winding level does not properly collapse in presence of an output short). here, when the internal 0.8 v maximum peak current limit is activated, the timer capacitor is charged. if the fault disappears, the timer capacitor is discharged by a current equal to the charging current. if the timer reaches completion while the error flag is still present, the controller stops the pulses and goes into a latch ? off phase, operating in a low ? frequency burst ? mode via a triple hiccup operation. to limit the fault output power, a divide ? by ? three circuitry is installed on the v cc pin and requires 3 times a start ? up sequence before attempting to restart on version b. as soon as the fault disappears, the smps resumes operation. the latch ? off phase can also be initiated, more classically, when v cc drops below vcc min . on version a, the fault is latched. ? brownout : the NCP1336 includes a brownout circuit which safely stops the controller in case the input voltage is too low. restart occurs via a complete startup sequence (latch reset and soft ? start).
NCP1336a/b http://onsemi.com 10 application information the NCP1336 has two operating modes: quasi resonant operation and vco operation. the operating mode is fixed by the fb voltage: ? quasi ? resonant operation occurs for fb voltage higher than 0.8 v (fb decreasing) or higher than 1.6 v (fb increasing) which correspond to high output power and medium output power. during quasi ? resonant operation, the operating valley (1 st , 2 nd , 3 rd or 4 th ) is fixed by the fb voltage which is compared internally to several voltage references corresponding to the different valleys. there is a wide hysteresis on each valley, allowing the controller to adjust the output power by the current ? mode control without jumping between valleys. the peak current is variable and is set by the fb voltage divided by 4. ? vco operation occurs for fb voltage lower than 0.8 v (fb decreasing) or lower than 1.6 v (fb increasing). this corresponds to low output power. during vco operation, the peak current is fixed to 25% of its maximum value and the frequency is variable. the frequency is set by the end of charge of ct capacitor. this capacitor is charged with a constant current source and the capacitor voltage is compared to an internal threshold fixed by fb voltage. when this capacitor voltage reaches the threshold the capacitor is rapidly discharged down to 0 v and a new period start. startup NCP1336 includes a high voltage startup circuitry that derives current from the bulk line to charge the v cc capacitor. when the power supply is first connected to the mains outlet, the internal current source is biased and charges up the v cc capacitor. when t he voltage on this v cc capacitor reaches the vcc on level, the current source turns off, reducing the amount of power being dissipated. at this time, the controller is only supplied by the v cc capacitor, and the auxiliary supply should take over before v cc collapses below vcc min . figure 3 shows the internal arrangement of this structure: figure 3. startup circuitry: the current source brings v cc above 15 v and turns off - + + + hv vcc gnd ic1 or ic2 hv vcc on vcc min in some fault situations, a short ? circuit can purposely occur between v cc and gnd. in high line conditions (v hv = 370 vdc) the current delivered by the startup device will seriously increase the junction temperature. for instance, since ic2 equals 3 ma (the min corresponds to the highest t j ), the device would dissipate 370 v x 3 ma = 1.11 w. to avoid this situation, the controller includes a novel circuitry made of two startup levels, ic1 and ic2. at power ? up, as long as v cc is below a certain level (0.7 v typ.), the source delivers ic1 (around 300 a typical), then, when v cc reaches 0.7 v, the source smoothly transitions to ic2 and delivers its nominal value. as a result, in case of short ? circuit between v cc and gnd, the power dissipation will drop to 370 v x 300 a = 111 mw. figure 4 portrays this particular behavior: figure 4. the dual level startup current source v cc
NCP1336a/b http://onsemi.com 11 the first startup period is calculated by the formula, cv = it which implies a 22 f x 0.9 v / 150 a = 132 ms startup time for the first sequence. the second sequence is obtained by changing i to 3 ma (worst case calculation) with v = 15 v ? 0.9 v = 14.1 v, which finally leads to a second startup time of 22 f x 14.1 v / 3 ma = 103 ms. the total startup time becomes 103 ms + 132 ms = 235 ms. please note that this calculation is approximated by the presence of the knee in the vicinity of the transition. as soon as v cc reaches vcc on , drive pulses are delivered on pin 9 and the auxiliary winding increases the voltage on the v cc pin. at the same time, the controller smoothly ramps up the peak current to i max (0.8 v / r sense ) which is reached after a typical 5 ms soft ? start period. as soon as the cs voltage reaches 0.8 v = i limit1 , the internal error flag ipflag is asserted. when the error flag is asserted, the current source on pin 3 is activated and charges up the capacitor connected to this pin. if the error flag is still asserted when the timer capacitor has reached the threshold level vtimfault, then the controller assumes that the power supply has really undergone a fault condition and immediately stops all pulses to enter a safe burst operation. figure 5 depicts the v cc evolution during a proper startup sequence, showing the state of the error flag: figure 5. an error flag gets asserted as soon as the current setpoint reaches its upper limit (0.8 v/r sense ). here the timer lasts 50 ms, a 100 nf capacitor being connected to pin 3. NCP1336 operation the valley detection is done by monitoring the voltage of the auxiliary winding of the transformer. the typical detection level is fixed at 55 mv . when a valley is detected, the decimal counter is incremented. the operating valley (1 st , 2 nd , 3 rd or 4 th ) is determined by the fb voltage. as fb voltage decreases or increases, the valley comparators toggle one after another to select the proper valley. the activation of an ?n? valley comparator disables the ?n+1? or ?n ? 1? valley comparator (depending if fb increases or decreases) and enables the corresponding ?n? output of the decimal counter. figure 6 shows the internal arrangement of the valley selection circuitry.
NCP1336a/b http://onsemi.com 12 figure 6. valley selection and vco internal schematic + ? + ? + ? + ? fb ct ict 1st 2nd 3rd 4th vco + ? + ? zcd laux 10 v esd vth drv tblank decimal counter 1 demag clk s r q leakage blanking vdd vdd rpullup rst drv 234 q ct setpoint discharge ct cs comparator time out v fbth when an ?n? valley is asserted by the valley selection circuitry, the controller is locked in this valley until the fb voltage decreases of 0.6 v (?n+1? valley activates) or increases of 0.8 v (?n ? 1? valley activates). the peak current adjusts to deliver the necessar y output power (see figure 7 and figure 8). each comparator has a hysteresis of 600 mv that helps to stabilize the valley selection in case of oscillations on fb voltage. figure 7. peak current setpoint and selected valley vs. fb voltage when fb voltage decreases
NCP1336a/b http://onsemi.com 13 figure 8. selected valley according to fb state as the output load decreases (fb voltage decreases), the valleys are incremented from the first to the fourth. when the fourth valley is reached, if fb voltage further decreases below 0.8 v, the controller enters vco mode as in ncp1351. during vco operation, the peak current is frozen to 25% of maximum peak current: the switching frequency expands to deliver the necessary output power. this allows achieving very low standby power consumption. figure 9 shows a simulation case where the output current of a 19 v / 60 w adapter decreases from 2.5 a to 0.5 a. no instability is seen during the valley transitions (figures 10, 11, 12 and 13.) figure 9. output load decreases from 2.5 a to 0.5 a at v in = 120 vdc for a 19 v / 60 w adapter
NCP1336a/b http://onsemi.com 14 figure 10. zoom 1: 1st to 2nd valley transition figure 11. zoom 2: 2nd to 3rd valley transition 2 feedback 3 vdrain 4 vct 600m 1.00 1.40 1.80 2.20 feedback in volts plot2 2 ? 100 0 100 200 300 vdrain in volts plot3 3 6.41m 6.43m 6.45m 6.47m 6.49m time in seconds 0 1.00 2.00 3.00 4.00 vct in volts plot4 4 v drain v fb v ct 2 feedback 3 vdrain 4 vct 600m 1.00 1.40 1.80 2.20 feedback in volts plot2 2 ? 100 0 100 200 300 vdrain in volts plot3 3 7.135m 7.153m 7.170m 7.188m 7.205m time in seconds 0 1.00 2.00 3.00 4.00 vct in volts plot4 4 v drain v fb v ct
NCP1336a/b http://onsemi.com 15 figure 12. zoom 3: 3rd to 4th valley transition figure 13. zoom 4: 4th valley to vco mode transistion 2 feedback 3 vdrain 4 vct 600m 1.00 1.40 1.80 2.20 feedback in volts plot2 2 ? 100 0 100 200 300 vdrain in volts plot3 3 7.902m 7.917m 7.932m 7.946m 7.961m time in seconds 0 1.00 2.00 3.00 4.00 vct in volts plot4 4 v drain v fb v ct 2 feedback 3 vdrain 4 vct 600m 1.00 1.40 1.80 2.20 feedback in volts plot2 2 ? 100 0 100 200 300 vdrain in volts plot3 3 8.24m 8.26m 8.29m 8.31m 8.34m time in seconds 0 1.00 2.00 3.00 4.00 vct in volts plot4 4 v drain v fb v ct
NCP1336a/b http://onsemi.com 16 time out in case of extremely damped free oscillations, the zcd comparator can be unable to detect the valleys. consequently, the decimal counter clock is in low state and the drive pulses stops. to avoid such situation, NCP1336 integrates a time out function that acts as a clock for the decimal counter. the controller thus continues its normal operation. to avoid having a too big step in frequency, the time out duration is set to 5.25 s. figures 15 and 16 detail the time out operation. figure 14. time out circuit - + + 10 v esd zcd laux vth 3 s pulse drv rst demag decimal counter clk 4 3 2 1 leakage blanking - + + vdd 5 s timeout 100 ns
NCP1336a/b http://onsemi.com 17 4 3 14 12 15 16 4.79m 4.81m 4.83m 4.85m 4.87m time in seconds 17 4 3 14 18 15 16 7.08m 7.12m 7.16m 7.20m 7.24m time in seconds 17 figure 15. time out operation chronogram figure 16. time out operation chronogram continued high low high low high low high low high low high low high low high low the 3rd valley is validated the 3rd valley is not detected by the zcd comp timeout adds a pulse to account for the missing 3rd valley the 2nd valley is detected by the zcd comparator the 4th valley is validated timeout adds 2 pulses to account for the missing 3rd and 4th valley demag vth 3rd 2nd zcdcomp timeout clk demag vth 3rd 4th zcdcomp timeout clk
NCP1336a/b http://onsemi.com 18 vco mode vco operation occurs for fb voltage lower than 0.8 v (fb decreasing), or lower than 1.6 v (fb increasing). this corresponds to low output power. during vco operation, the peak current is fixed to 25% of its maximum value and the frequency is variable and expands as the output power decreases. the frequency is set by the end of charge of ct capacitor. this capacitor is charged with a constant current source and the capacitor voltage is compared to an internal threshold fixed by fb voltage (see figure 6). when this capacitor voltage reaches the threshold, the capacitor is rapidly discharged down to 0 v and a new period start. the internal threshold is inversely proportional to the fb voltage. the relationship between v fbth and v fb is: v fbth = 6.5 ? (10/3) v fb . when v fb is lower than 0.3 v, ct voltage is clamped to vct max = 5.5 v. figure 17 shows the vco mode at works . 1 iout 2 vct 3 v(fbint:x1) 5 drv 0 200m 400m 600m 800m iout in amperes plot1 1 ? 1.00 1.00 3.00 5.00 7.00 v(fbint:x1),vct in volts plot2 2 3 7.57m 7.78m 7.99m 8.20m 8.40m time in seconds ? 10.0 0 10.0 20.0 30.0 drv in volts plot3 5 drv ct, fb threshold i out figure 17. in vco mode, as the power output decreases the frequency expands figure 18. fault timer schematic - + - + i limit + i timerc timer vdd opp cs fb/4 pwm comparator max ip comparator ilimit + vopp r s q q r s q q + - drv ipflag pwm reset vcc management c timer i timerd pnok fault hv vcc vtimfault + +
NCP1336a/b http://onsemi.com 19 short ? circuit or overload mode figure 18 shows the implementation of the fault timer. when the current in the mosfet is higher than, ?max (0.8 v / r sense ) ip? comparator trips and the timer capacitor is charged by itimerc current source. when the current comes back within safe limits, ?max ip? comparator becomes silent and the pwm comparator triggers the discharge of the timer capacitor. if ?ipflag? and pwmreset occur at the same time, the pwmreset signal is the strongest and the capacitor is discharged. 3 v(ipflag:x1) 4 v(pwm:x1) 8 feedback 9 vtimer ? 200m 200m 600m 1.00 1.40 vtimer in volts 1.80 2.20 2.60 3.00 3.40 feedback in volts plot1 8 9 6.13m 6.37m 6.60m 6.84m 7.08m time in seconds plot2 4 3 ipflag pwmreset v timer v fb low high low high figure 19. timer operating chronograms there can be various events that force a fault on the primary side controller. we can split them in different situation, each having a particular configuration: 1. the converter regulates but the auxiliary winding collapses: this is a typical situation linked to the usage of a constant ? current / constant ? voltage (cc ? cv) type of controller. if the output current increases, the voltage feedback loop gives up and the current loop takes over. it means that v out goes low but the feedback loop is still closed because of the output current monitoring. therefore, seen from the primary side, there is no fault. however, there are numerous charger applications where the output voltage shall not go below a certain limit, even if the current is controlled. to cope with this situation, the controller features a precise under ? voltage lockout comparator biased to a vcc min level. when this level is crossed, whatever the other pin conditions, pulses are stopped and the controller enters the safe hiccup mode, trying to re ? start. figure 20 shows how the converter will behave in this situation. if the fault goes away, the smps resumes operation. 2. in the second case, the converter operates in regulation, but the output is severely overloaded. however, due to the bad coupling between the power and the auxiliary windings, the controller v cc does not go low. the peak current is pushed to the maximum, the error flag ipflag is consequently asserted and the timer starts to count. upon completion, all pulses are stopped and triple ? startup hiccup mode is entered for version b. if the fault goes away, the smps resumes operation (figure 21). for version a, when the timer finishes counting, the pulses stop and the circuit stays latched until the user cycles down the power supply (figure 22). 3. another case exists where the short ? circuit makes the auxiliary level go below vcc min . in that case, the timer length is truncated and all pulses are stopped. the triple hiccup fault mode is entered and the smps tries to re ? start. when the fault is removed, the smps resumes operation.
NCP1336a/b http://onsemi.com 20 figure 20. first fault mode case, the auxiliary winding collapses but feedback is still there figure 21. short ? circuit case where vaux does not collapse on version b figure 22. short ? circuit case where vaux does not collapse on version a
NCP1336a/b http://onsemi.com 21 figure 23. this case is similar to a short ? circuit where v aux does collapse the recurrence in hiccup mode can easily be adjusted by either reducing the timer or increasing the v cc capacitor. figure 24 details the various time portion a hiccup is made of: figure 24. the burst period is ensured by the v cc capacitor charge / discharge cycle if by design we have selected a 22 f v cc capacitor, it becomes easy to eva luate the burst period and its duty ? cycle. this can be done by properly identifying all time events on figure 8 and applying the classical formula: t c v i ? t 1 : i = 3 ma, v= 15 v ? 9 v = 6 v t 1 = 44 ms ? t 2 : i = icc3 = 600 a, v= 15 v ? 9 v = 6 v t 2 = 220 ms the total period duration is thus the sum of all these events which leads to t hiccup = 572 ms. if t fault = 50 ms, then our burst duty ? cycle equals 50 ms / (572 ms + 50 ms) 8%, which is good. should the user like to further decrease or, to the contrary, increase this duty ? cycle, changing the v cc capacitor is an easy job.
NCP1336a/b http://onsemi.com 22 over voltage / over temperature protection the otp and ovp pins feature circuitries to protect the circuit against high temperature and high voltage (see figure 25). figure 25. pin latch circuitry ovp iotp votp + 20 s filter - + - + vovp + r bias end of soft ? start otp vdd vcc t otp a current flows out of the otp pin into the ntc resistor, thus imposing a voltage on the otp pin. when the temperature increases, the ntc?s resistance reduces (for example, at 110 c, r ntc = 8.8 k instead of 470 k at 25 c) and the voltage on the otp pin decreases until it reaches v otp : the comparator trips and latches ? off the controller. to reset the controller, the user must unplug and re ? plug the power supply. during start ? up and soft ? start, the output of the otp comparator is masked to allow for the voltage on the otp pin to grow if a capacitor is installed across the ntc for filtering purposes. ovp when v cc increases (ovp), a current starts to flow in the zener (which much be biased externally), and the voltage on the ovp pin starts to increase. when this voltage reaches v ovp , the circuit immediately stops pulsing and stays latched until the user cycles down the power supply. the reset occurs if v cc drops below 5 v (or brownout is detected). figures 26 and 27 details the operating diagrams in case of an over temperature and an overvoltage event. figure 26. operating diagrams in case of an over temperature v otp(pin) ambient temperature increases v otp
NCP1336a/b http://onsemi.com 23 figure 27. operating diagrams in case of an over voltage v ovp(pin) v ovp over power protection the implementation of over power compensation in NCP1336 is described by figure 28. a negative voltage applied on the opp pin directly affects the precise maximum peak current reference. figure 28. the internal opp circuitry implemented on NCP1336 + - r upper r lower opp 0.8 v + aux cs leading edge blanking fb/4 - + + esd protection 0.8 v + vopp ipflag pwmreset r sense by connecting the opp pin through a resistor divider to an auxiliary winding with flyback polarity, where a negative voltage proportional to the input voltage appears during the on ? time, the maximum peak current setpoint is simply decreased according to v in , following figure 29.
NCP1336a/b http://onsemi.com 24 figure 29. peak current setpoint variation vs. opp pin voltage v hv by adding a zener diode in series with the resistor divider, the user has the choice to adjust the level at which the opp is applied to the power chip. design example let us assume we need a current setpoint reduction of 25% at 370 vdc, which corresponds to a sense voltage of 600 mv. we thus need to apply 600 mv ? 800 mv = ? 200 mv on opp pin to perform the expected compensation. knowing that the voltage that appears on the auxiliary winding during the on ? time is ? n p,aux v in , with n p,aux the auxiliary to primary turn ratio of the transformer (n p,aux = n aux /n p ), we can simply calculate the ratio of the resistor divider: r upper r lower n p,aux v in v opp v opp assuming the turn ratio of the transformer is n p,aux = 0.25, we obtain: r upper r lower 0.25 370 ( ? 0.2) ? 0.2 461.5 with r upper = 470 k and r lower = 1 k for instance, the opp function is performed with negligible power wasted in the resistor divider. brownout the NCP1336 features a brownout pin to protect the power supply against low input voltage condition. this pin permanently monitors a fraction of the bulk voltage through a voltage divider. when this image of bulk voltage is below the vbo threshold, the controller stops switching. when the bulk voltage comes back within safe limits, the circuit goes through a new startup sequence including soft ? start and restarts switching (figure 30). the hysteresis on brownout pin is implemented with a low side current source sinking 10 a when the brownout comparator is low (v bulk < v bulkon ). figure 30. brownout operating chronograms
NCP1336a/b http://onsemi.com 25 figure 31. brownout circuitry + - hv ? bulk r upper r lower bo ibo vbo + bo comp bo reset 20 s noise delay ibo ?on? if bo comp ?low? ibo ?off? if bo comp ?high? the following equations show how to calculate the resistors for bo pin. first of all, select the bulk voltage value at which the controller must start switching (v bulkon ) and the bulk voltage for shutdown (v bulkoff ). then use the following equation to calculate r upper and r lower . r lower vbo(v bulkon v bulkoff ) i bo (v bulkoff vbo) r upper r lower (v bulkoff v bo ) vbo design example v bo = 0.8 v i bo = 10 a we select: v bulkon = 120 v, v bulkoff = 60 v r lower vbo (v bulkon v bulkoff ) i bo (v bulkoff vbo) 0.8 v (120 v 60 v) 10 a (60 v 0.8 v) 81.1 k r upper r lower (v bulkoff v bo ) v bo 81.1 k (60 v 0.8 v) 0.8 v 6m ordering information device package type shipping ? NCP1336adr2g so ? 14 less pin 13 (pb ? free) 2500 / tape & reel NCP1336bdr2g so ? 14 less pin 13 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCP1336a/b http://onsemi.com 26 package dimensions soic ? 14 nb, less pin 13 case 751an issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m dim min max millimeters d 8.55 8.75 e 3.80 4.00 a 1.35 1.75 b 0.35 0.49 l 0.40 1.25 e 1.27 bsc a3 0.19 0.25 a1 0.10 0.25 m 0 7 h 5.80 6.20 h 0.25 0.50 6.50 13x 0.58 13x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP1336/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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